1. Field of the Invention
The present invention relates to a logic unit and integrated circuit for clearing interrupts, and in particular to a logic unit and integrated circuit for efficiently clearing interrupts generated in a clock domain operating at a lower frequency than the clock domain in which the processor processing the interrupt is operating.
2. Description of the Prior Art
It is known to provide a processor for performing a number of processing operations, including the processing of interrupts, and to couple that processor via one or more buses to a number of logic units. The bus may be arranged to operate in a first clock domain, and a logic unit may be used to interface between the bus and a device operating in a second clock domain. As an example, the logic unit may form a peripheral interface for interfacing between the bus and a peripheral device. In many implementations, the peripheral device will use a peripheral clock which is significantly slower than the clock used to clock the bus. Considering a specific example, the bus may be operating in a first clock domain with a bus clock operating at 100 MHz. In contrast, a peripheral interface such as a xe2x80x9cUniversal Asynchronous Receive and Transmitxe2x80x9d (UART) logic unit may be arranged to use a 1.8432 MHz clock used in the clock domain of the peripheral device (the second clock domain).
A logic unit, such as a UART, will receive signals from its associated peripheral device, and when required will generate an interrupt signal in the slow clock domain. This interrupt signal will be passed over the bus to the processor, where the processor will then process that interrupt. At an appropriate point during processing of the interrupt, for example when the interrupt is received by the processor, or when the interrupt has been processed by the processor, the processor will typically be arranged to issue a clear request signal to cause the interrupt to be cleared. However, it will be appreciated that it will take several clock cycles in the high speed clock domain of the processor to clear the interrupt, since the interrupt must be cleared in the slow clock domain of the peripheral device. This causes a problem in that, if the circuitry is not designed correctly, it is possible for the processor to have written the clear command and then to have returned to normal processing, only to be re-interrupted by the original interrupt signal, since the interrupt is still present in the slow clock domain.
One way to avoid this problem is to halt the processor until the interrupt is cleared in the slow clock domain. However, it will be appreciated that this approach will waste processor clock cycles, thereby impacting on the efficiency of the processor.
Accordingly, it is desirable to provide a technique for more efficiently clearing interrupts generated in the slow clock domain.
Viewed from a first aspect, the present invention provides a logic unit for coupling to a bus operating in a first clock domain, and for interfacing between the bus and a device operating in a second clock domain, the frequency of the second clock domain being less than the frequency of the first clock domain. the logic unit comprising: an interrupt source, responsive to a signal issued by the device, for asserting a first interrupt signal in the second clock domain; output logic, responsive to the first interrupt signal, to output a second interrupt signal via the bus to a processor operating in the first clock domain, the processor being arranged to process the interrupt indicated by the second interrupt signal, and to issue a clear request signal at a predetermined point during processing of the interrupt; clear generation logic arranged, whilst the first interrupt signal is asserted, to be responsive to receipt of the clear request signal to assert a clear signal to the interrupt source and to assert a control signal to the output logic; the output logic being responsive to receipt of the control signal to stop outputting the second interrupt signal; the interrupt source being responsive to the clear signal to de-assert the first interrupt signal, the de-assertion of the first interrupt signal causing a clear acknowledge signal to be generated; the clear generation logic being responsive to the clear acknowledge signal to de-assert the clear signal.
In accordance with the present invention, when the logic unit generates a first interrupt signal in the second clock domain, output logic is arranged to conditionally output that first interrupt signal as a second interrupt signal which is then sent via the bus to a processor, the processor being arranged to process the interrupt and to issue a clear request signal at a predetermined point during processing of the interrupt. As mentioned earlier, this predetermined point may be any suitable point during processing of the interrupt, and in preferred embodiments the clear request signal is sent by the processor once the interrupt has been processed. Alternatively, however. it will be appreciated that the clear request signal may be issued upon receipt of the interrupt by the processor.
Further, clear generation logic is provided which is responsive to receipt of the clear request signal, to assert a clear signal to the interrupt source and to assert a control signal to the output logic. The control signal causes the output logic to stop outputting the second interrupt signal,. and hence the processor is clear to continue with other processing. At this stage, the first interrupt signal is still being asserted by the interrupt source. However, the clear signal is used by the interrupt source to de-assert the first interrupt signal. A clear acknowledge signal is then generated to indicate when the first interrupt signal has been de-asserted. Whilst this de-assertion of the first interrupt signal is taking place, the clear generation logic continues to assert the clear signal. However, upon receipt of the clear acknowledge signal, the clear generation logic is arranged to de-assert the clear signal.
By the above approach, it will be seen that the second interrupt signal ceases to be output by the logic unit upon receipt of the clear request signal from the processor, the clear request signal also causing a clear signal to be asserted by the logic unit to the interrupt source. At this point, the processor can then return to performing further processing operations whilst the logic unit takes responsibility for then clearing the first interrupt signal using the asserted clear signal. Once the first interrupt signal in the second clock domain is de-asserted, a clear acknowledge signal is then generated to cause the clear signal to be de-asserted, to thereby return the relevant logic to its original state.
It will be appreciated that the clear acknowledge signal may be a separate signal generated once the first interrupt signal is de-asserted. However, in preferred embodiments, the clear generation logic is arranged to receive the first interrupt signal, and the de-asserted first interrupt signal forms the clear acknowledge signal. This provides simplification in the design, since the interrupt source output is also used directly as the clear acknowledge signal. Hence, the first interrupt signal being reset is used as a clear acknowledge signal to the clear generation logic, to enable the clear generation logic to then de-assert the clear signal being used to cause the first interrupt signal to be reset.
It will be appreciated that the clear generation logic may be embodied in a variety of ways. However, in preferred embodiments, the clear generation logic is arranged to operate in the first clock domain, and the logic unit further comprises resynchronisation logic for resynchronising the first interrupt signal to the first clock domain.
In preferred embodiments, the clear generation logic is arranged to receive the clear request signal as a set signal and the clear acknowledge signal as a rest signal, whereby the clear generation logic is arranged to assert the clear signal upon receipt of the clear request signal, and to maintain the clear signal until the clear acknowledge signal is received, at which point the clear signal is de-asserted.
In preferred embodiments, a xe2x80x9csetxe2x80x9d or xe2x80x9cassertedxe2x80x9d signal has a logic xe2x80x9c1xe2x80x9d value, and a xe2x80x9cresetxe2x80x9d or xe2x80x9cde-assertedxe2x80x9d signal has a logic xe2x80x9c0xe2x80x9d value, although it will be appreciated by those skilled in the art that this may readily be reversed, depending on the specific implementation.
In preferred embodiments, the clear generation logic comprises a first logic element arranged to receive the clear request signal and the output of the clear generation logic and a second logic element arranged to receive the output of the first logic element and the clear acknowledge signal, the two logic elements being arranged such that the clear signal is asserted upon receipt of the clear request signal, and is maintained irrespective of whether the clear request signal is maintained until such time as the clear acknowledge signal is received. It will be appreciated that the first and second logic elements may take a variety of forms, and indeed may be embodied within a single piece of logic. However, in preferred embodiments, the first logic element is a logical OR gate, and the second logic element is a logical AND gate.
It will be appreciated that the output logic may be embodied in a variety of ways. However, in preferred embodiments, the output logic comprises a logic gate arranged to conditionally output the first interrupt signal as the second interrupt signal dependent on whether the control signal is asserted.
In accordance with a first embodiment, the clear signal forms the control signal, and the output logic comprises an inverter for inverting the control signal, and a logical AND gate for receiving the first interrupt signal and the inverted control signal, whereby the first interrupt signal is output as the second interrupt signal until the clear signal is asserted, at which point the logical AND gate stops outputting the second interrupt signal.
In an alternative embodiment. the clear signal forms the control signal, and the output logic comprises a logical NOR gate for receiving an inverted version of the first interrupt signal and the control signal, whereby the first interrupt signal is output as the second interrupt signal until the clear signal is asserted, at which point the logical NOR gate stops outputting the second interrupt signal.
In a further embodiment, the clear generation logic is arranged to generate the control signal as an inverted version of the clear signal, and the output logic comprises a logical AND gate for receiving the first interrupt signal and the control signal, whereby the first interrupt signal is output as the second interrupt signal until the clear signal is asserted, at which point the logical AND gate stops outputting the second interrupt signal.
It will be appreciated by those skilled in the art that the above three examples of the output logic are not the only possible implementations. and that any other arrangement may be used to cause the first interrupt signal to be conditionally output as the second interrupt signal dependent on the assertion of the control signal.
In certain implementations, it is possible that any particular logic unit may generate interrupt signals for a variety of reasons. To enable the processor to correctly process the interrupt, it may need to determine the type of interrupt that has occurred. Accordingly, in preferred embodiments, the logic unit further comprises a register for storing as interrupt status information the first interrupt signal as resynchronised to the first clock domain, the register being accessible by the processor during processing of the interrupt. Preferably, a separate register is provided for each type of interrupt, and accordingly the processor can determine based on the presence of interrupt status information within a particular register the type of interrupt that has occurred.
Viewed from a second aspect, the integrated circuit comprises: a processor for processing interrupts; a logic unit in accordance with the first aspect of the present invention; and a bus for coupling the logic unit and the processor.
In preferred embodiments. the integrated circuit further comprises an interrupt controller coupled to the bus, and arranged to receive the second interrupt signal from the output logic, and to determine when to pass the interrupt to the processor for processing. It will be appreciated that the interrupt controller may be integrated as part of the processor, or may be formed as a separate unit. In preferred embodiments, the interrupt controller is a separate unit to the processor, and is arranged to enable or disable the interrupts, and optionally to prioritise the various interrupt signals destined for the processor.